.LISTMAC .MACRO ADDI subi @0, -(@1) .ENDMACRO ;skip next instruction if not equal to zero .MACRO skipne .SET _skipne = PC+2 brne _skipne .ENDMACRO ;skip next instruction if carry set .MACRO skipcs .SET _skipcs = PC+2 brcs _skipcs .ENDMACRO ;skip next instruction if carry clear .MACRO skipcc .SET _skipcc = PC+2 brcc _skipcc .ENDMACRO ;skip next instruction if equal to zero .MACRO skipeq .SET _skipeq = PC+2 breq _skipeq .ENDMACRO ;skip next instruction if lower .MACRO skiplo .SET _skiplo = PC+2 brlo _skiplo .ENDMACRO ;skip next instruction if half carry set .MACRO skiphs .SET _skiphs = PC+2 brhs _skiphs .ENDMACRO ;skip next instruction if half carry clear .MACRO skiphc .SET _skiphc= PC+2 brhc _skiphc .ENDMACRO ;skip next instruction if T set .MACRO skipts .SET _skipts = PC+2 brts _skipts .ENDMACRO ;skip next instruction if T clear .MACRO skiptc .SET _skiptc = PC+2 brtc _skiptc .ENDMACRO ;skip next instruction if minus .MACRO skipmi .SET _skipmi = PC+2 brmi _skipmi .ENDMACRO ;skip next instruction always .MACRO skipnext .SET _skipnext = PC+2 rjmp _skipnext .ENDMACRO ;wait two cycles but waste only one instruction .MACRO doublenop .SET _doublenop = PC+1 rjmp _doublenop .ENDMACRO ;compare Port bit with T, and branch to @2 if are not equal .MACRO cpeqPortBit sbic @0,@1 .SET _cpPortBit1 = PC+3 rjmp _cpPortBit1 brts @2 .SET _cpPortBit0 = PC+2 rjmp _cpPortBit0 brtc @2 .ENDMACRO ;compare Port bit with T, and branch to @2 if are equal .MACRO cpnePortBit sbic @0,@1 .SET _cpPortBit1 = PC+3 rjmp _cpPortBit1 brtc @2 .SET _cpPortBit0 = PC+2 rjmp _cpPortBit0 brts @2 .ENDMACRO ;compare Register bit with T, and branch to @2 if are not equal .MACRO cpeqRegBit sbrc @0,@1 .SET _cpRegBit1 = PC+3 rjmp _cpRegBit1 brts @2 .SET _cpRegBit0 = PC+2 rjmp _cpRegBit0 brtc @2 .ENDMACRO ;compare Register bit with T, and branch to @2 if are equal .MACRO cpneRegBit sbrc @0,@1 .SET _cpRegBit1 = PC+3 rjmp _cpRegBit1 brtc @2 .SET _cpRegBit0 = PC+2 rjmp _cpRegBit0 brts @2 .ENDMACRO